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/ Synthesis Solutions / Synthesis Solutions by Exemplar Logic (Exemplar Logic).iso / exemplar.dxr / 00445_Bitmap_galprs14 (.png)

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Bitmap Image  |  1997-06-03  |  160KB  |  378x417  |  8-bit (218 colors)

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OCR: Logic Explorer ORCA Output Options Part: or2c1 10aJ160 Options Speed Grade: Max Fanin: Global Set Reset Man to Synchronous Registers: FD1 1S3IX FD1S3IX FD P3IZ FD P3JZ FD1S11_Q FD1S1J- PREP FERENCE OUTPUT FILE Directory: xemplar/galileo v3.2.5.sss/demo File Name: uart.prf Synthesis Switches: Do NOT Use DFFs with Clock Enable Do NOT Annotate Packing Information Do NOT Use Look Up Table Mapping Enable Mapping inn or2c10al160 FD153JX FD1S1 PREFERENCE deap

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